The present invention relates to very large scale integrated circuits, and to methods for fabrication thereof.
For many years there has been discussion of the problem of buried channel PMOS (p-channel) devices in scaled CMOS, due to the work function of the n+ poly gate normally used. As CMOS devices continue to scale down, the drain induced punchthrough problem becomes more serious. High tank doping concentrations must be used to prevent punchthrough from source to drain. For transistors with 0.5 micron gate lengths, concentrations in the 1E17 cm.sup.-3 range are required. Higher substrate doping will normally result in larger threshold voltage magnitude for inversion-mode transistors. When n+ POCI.sub.3 -doped polysilicon is used for the gates (as is conventional), the increased threshold voltage is not a problem for the n-channel transistor, because the work function difference between the n+ poly and the p-type tank works to reduce the high V.sub.T which would otherwise result from the high tank concentration. However, in the p-channel transistors, there is no such work function difference between the n+ poly and the n-type tank, so that the magnitude of the threshold voltage is very large: to obtain threshold voltages in the 0.8 V range, a boron threshold shifting implant is normally added, but this forms a shallow buried channel transistor. This increases subthreshold leakage of the device. In any case, it is generally believed that the buried channel design will not be satisfactory for 0.5 micron transistors.
That is, in a conventional scaled NMOS device, the channel (which might be, e.g., doped 4E16 p-type) will have a Fermi level close to the valence band edge, while the heavily doped n-type polysilicon gate has a Fermi level which is approximately at or above the conduction band edge. Thus, the difference between these two Fermi levels (or, equivalently, the difference between their work functions--work function is defined as the difference between the Fermi level and the potential of vacuum) defines a flat-band voltage of about 0.9 volts. If there were no flat-band voltage (no work function difference), the threshold voltage for the n-channel devices would be about 1.8 volts (for a 250 A gate oxide and 4E16 cm.sup.-3 channel doping), which is too high; but the 0.9 V flatband voltage (work function difference) means that the n-channel threshold voltage is reduced to about 0.9 V, which is advantageous. However, in the conventional scaled PMOS device no such work function difference exists (since the Fermi levels of both gate and channel will be close to the conduction band edge), and therefore the flatband voltage is approximately zero. This means that the high p-channel threshold voltage (e.g. 1.8 V) is not reduced by the flatband voltage, and therefore an implant must be used to permit the PMOS devices to function at all. This implant necessarily results in a buried channel device, which have inferior transistor characteristics, and in particular inferior turn-off characteristics.
This problem has been discussed for many years, and one long-proposed way to avoid this problem has been to use n+ polysilicon to form the gate level of the NMOS devices, and p+ polysilicon to form the gate level of the PMOS devices, within a single deposited level of polysilicon. In any such approach it will be necessary to perform some sort of masked implant or masked deposition step, to provide the distinct n+ and p+ regions of the polysilicon layer, but this is not difficult--for example, the source/drain implants can be used for this. The problem is how connections are to be made between the n+ and p+ polysilicon levels, and this has in general been the failing point of such proposed approaches. For example, it has been proposed to use silicide to make this connection, but the problem then arises, again, that counterdiffusion of dopants through the silicide occurs, so that the sheet resistance of the polysilicon in the neighborhood of an n+/silicide/p+ contact is increased by counter doping. On the other hand, if metal jumpers are used for this interconnection, that is very expensive in terms of area.
In addition to shrinking the transistor gate length, it is necessary to shrink all other dimensions to obtain high density. Thus, the distance between (1) the n-channel transistors with n+ poly and (2) the p-channel transistors with p+ poly will become extremely small. The problem caused by this shrink is that interdiffusion of the n+ and p+ dopants between the two types of transistors gates can occur. This problem is especially severe when the gates are clad with titanium disilicide in which both boron and phosphorus diffuse extremely rapidly. This interdiffusion will cause counterdoping of the gates and make it difficult to control the Fermi level in the poly gates.
One of the advantages of the present invention is a solution to the counter-doping problem by using TiN to connect poly to poly or to moat, preventing counterdiffusion through the local interconnect (which acts as a diffusion barrier).
In a sample process flow for this embodiment,
1. the polysilicon (or silicide, or polycide, or whatever silicon-bearing polycrystalline material is used for the gate level) is deposited undoped, and is patterned. PA0 2. A reachthrough implant is then performed to provide LDD regions. PA0 3. Sidewall oxides are deposited on the gate, and patterned source/drain implants (which also dope the polysilicon) are performed. PA0 4. Ti (1000 A) is deposited (e.g. by sputtering at room temperature) and furnace direct-reacted (at 675.degree. C.), to produce TiSi.sub.2 on the gates and moats and TiN elsewhere. PA0 5. The TiN is patterned, and the unwanted TiN removed. PA0 6. The TiSi.sub.2 and TiN layers receive an anneal (800.degree. C.). PA0 a substrate; PA0 a plurality of NMOS transistors having PA0 a plurality of PMOS transistors having PA0 a plurality of local interconnects electrically linking selected ones of said gates of said NMOS transistors to selected ones of said gates of said PMOS transistors in predetermined locations, said local interconnects comprising a large fraction of titanium nitride.
Thus, the present invention provides a structure wherein moat-to-moat interconnections, and interconnections linking p+ poly to n+ poly, are very conveniently formed using a very thin (e.g. 1000 Angstroms) layer of titanium nitride. This invention provides at least the following advantages:
1. Since titanium nitride is a very good diffusion barrier, problems of interdiffusion through the silicide are avoided. This is particularly advantageous where the local interconnect layer is used to connect a p+ moat region to an n+ polysilicon gate or to an n+ moat region in CMOS processing.
2. Titanium nitride local interconnects according to the present invention are most especially advantageous in providing local interconnect between an n+ polysilicon gate and a p-type moat region. Since the distances from gate to moat are typically much shorter than the n+ to p+ spacings, interdiffusion is a particularly acute problem here.
3. Since the titanium nitride local interconnect layer can be made extremely thin, the amount of additional vertical topography induced in subsequent unplanarized layers is minimal.
4. Since the titanium nitride layer is so thin, the etch used to remove it need not be anisotropic, which again simplifies processing.
5. Even a very thin titanium nitride layer can provide very low sheet resistances, of the order of five to ten ohms per square.
6. The titanium nitride local interconnect layer can also be utilized to provide a diffusion barrier in place for contacts. That is, contacts to moat can deposit metal on top of the titanium nitride layer rather than directly on silicon, so that interdiffusion between metal and silicon is effectively prevented. This simplifies the selection of interconnect metallization. In particular, use of non-aluminum metallization now becomes much more practical.
7. The overlap of the titanium nitride onto the field oxide means that the contact holes need not be perfectly aligned to the edge of the moat, but the contact hole can overlap onto the titanium nitride over the upper surface of the edge of the field oxide.
8. The present invention provides a local interconnect layer of such good conductivity that strapping can be avoided in some applications, and thus the present invention will permit the elimination of double-level metal (DLM) process steps in some processes, without any sacrifice of speed or area.
9. The number of second contacts in a layout can be reduced, since independent interconnection through the TiN layer can substitute for some metal interconnects.
10. The present process is inherently amenable to shared contacts, i.e. to contacts where contact is made between two interconnect layers and substrate at the same location. This permits designers additional flexibility.
11. The capability of overlapping moat contacts up onto the field oxide means that minimum geometry can be used for the source/drain regions in the moat.
12. The present invention permits connection between stages of CMOS logic to be accomplished without any contact holes, which provides advantages in area, speed, and yield.
13. The present invention performs all the functions of a full buried contact capability, without the degraded reproducibility of series resistance for ohmic contacts to p+ which commonly results from buried contact processes.
14. The present invention performs all the circuit functions of a full buried contact capability, without the problem of shorting to an underlying n+ region where a local connection from polysilicon to a p+ source/drain region.
15. The present invention permits fabrication of a submicron CMOS device wherein both n-channel and p-channel devices are surface channel devices, with no sacrifice in area.
16. The present invention permits fabrication of a submicron CMOS device wherein both n-channel and p-channel devices are surface channel devices, without requiring use of a metal layer to connect the n+ polysilicon gate layer to the p+ polysilicon gate layer.
17. The present invention permits fabrication of a submicron CMOS device having two conductivity types of polysilicon gates with no increase in area or degradation in speed, by connecting p+ to n+ gates over the tank boundaries, in what would otherwise be waste space in the circuit layout.
18. The present invention permits fabrication of a submicron CMOS device having two conductivity types of polysilicon gates without requiring ANY additional deposition, masking, etching, or (assuming that source/drain counterdoping is not used) implanting steps over those which would be used anyway to provide a clad-moat process with local interconnects (as disclosed and claimed in the parent application).
19. The present invention permits fabrication of a submicron CMOS device having two conductivity types of polysilicon gates without requiring implementation of any novel processing parameters which have not already been well demonstrated in CMOS fabrication.
According to the present invention there is also provided: An integrated circuit device comprising:
substantially crystalline channel regions consisting essentially of silicon and located near the surface of said substrate, and PA1 gates which are substantially polycrystalline and comprise a large fraction of silicon and are doped n-type; PA1 substantially crystalline channel regions consisting essentially of silicon and located near the surface of said substrate, and PA1 gates which are substantially polycrystalline and comprise a large fraction of silicon and are doped p-type; and